Method and system for reading from a m-byte memory utilizing a p

Details Method and system for reading from a m-byte memory utilizing a p Method and system for reading from a m-byte memory utilizing a p

1994-12-13

1997-02-11

Shah, Alpesh M.

Boots, shoes, and leggings

395855, 3642328, 3642600, 364DIG1, G06F 1300

Patent

active

056030410

ABSTRACT:
A method and system are disclosed for reading data from an m-byte memory device utilizing a processor having an n-byte data bus, where m is less than or equal to n, which do not require the processor to support special bus cycles, bus select signals, or dynamic bus sizing. Responsive to an initiating signal from the processor to an interface controller, a plurality of data latches are initialized by a control signal. An address counter is also initialized. The memory device is activated by a control signal. Latching of data by one of the plurality of data latches is enabled. Data associated with an address indicated by the address counter is then latched from the memory device utilizing the enabled data latch. The address counter is incremented. The enabling, latching, and incrementing steps are repeated until n bytes of data are latched. When n bytes of data are latched, the processor is signaled that n bytes of data are valid to read. The processor then reads data from all of the plurality of data latches during a standard read cycle. Thereafter, output from the plurality of data latches is disabled. A burst reading mode is also supported that includes a step, prior to disabling output from the data latches, of responsive to a signal from the processor, repeating the reading step t times in t successive bus cycles, where t is characteristic of a burst transfer size required on initial program load by a cache within the processor.

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