Interface circuit having zero latency buffer memory and cache me

Details Interface circuit having zero latency buffer memory and cache me Interface circuit having zero latency buffer memory and cache me

1994-04-06

1997-04-22

Harrell, Robert B.

G06F 1314

Patent

active

056237006

ABSTRACT:
A caching disk controller is provided which includes a bus bridge that forms an interface between a memory of the disk controller and a host computer. The caching disk controller further includes a SCSI processor for controlling the transfer of data from a SCSI disk drive to the memory via a local bus. A zero latency DMA controller embodied within the bus bridge snoops the local bus as data is being transferred from the SCSI disk drive to the memory, and thereby allows the data to be sequentially latched within a data FIFO of the bus bridge concurrently with its transfer into the memory. As a result, the requested data may be advantageously provided from the bus bridge to the host computer with reduced delay, while the data continues to be stored within the memory to accommodate high hit rates during subsequent transfers.

REFERENCES:
patent: 4835686 (1989-05-01), Furuya et al.
patent: 5170299 (1992-12-01), Moon
patent: 5241546 (1993-08-01), Peterson et al.
patent: 5255136 (1993-10-01), Machado et al.

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