Semiconductor device including a potential drawing portion...

Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal

Reexamination Certificate

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Reexamination Certificate

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06924537

ABSTRACT:
A first semiconductor substrate (3) is so formed as to surround a periphery of a region between an upper substrate (1) and a lower substrate (11) like an outer peripheral frame, a potential drawing portion (31) of the first semiconductor substrate (3) is formed at a corner portion thereof and an area of the corner portion of the first semiconductor substrate (3) including the potential drawing portion (31) is made equal to or less than an area of each of potential drawing portions (36a, 36b, 40) of other semiconductor substrates (5, 7, 9), to achieve reduction in chip size. A conductive layer is formed on a surface of the upper substrate (1) or the like and the conductive layer is fixed to a fixed voltage such as a ground potential. This conductive layer or the like shields the semiconductor substrates against disturbance such as proximity of other substances, static electricity or radio wave hindrance.

REFERENCES:
patent: 4391032 (1983-07-01), Schulte
patent: 5349858 (1994-09-01), Yagi et al.
patent: 5545912 (1996-08-01), Ristic et al.
patent: 5-142252 (1993-06-01), None
patent: 5-340961 (1993-12-01), None
patent: 10-104265 (1998-04-01), None
Wolf and Tauber, “Silicon Processing for the VLSI Era, vol. 2—Process Integration,” Lattice Press, 2000, p. 851-852.

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