Boots – shoes – and leggings
Patent
1996-01-24
1997-04-22
Geckil, Mehmet B.
Boots, shoes, and leggings
39520019, 364DIG1, 364229, 3642292, 3642319, 3642396, 364240, 3642402, G06F 1300
Patent
active
056236891
ABSTRACT:
A parallel processor system is composed of N processors, N memories and the interconnection where N.times.N data buffers are two-dimensionally placed. Each data buffer provides a data memory with an empty signal and an AND gate. Each memory outputs the transmit completion signal. This signal is input into the corresponding N data buffers and is ANDed with the corresponding empty signal. Each processor inputs the transfer completion signal. This signal is produced by logical-OR among outputs of the AND gates of the corresponding N data buffers. By monitoring the transfer completion signal, each processor recognizes the end of data transfer as data transmission to the corresponding processor ends.
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Geckil Mehmet B.
Matsushita Electric - Industrial Co., Ltd.
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