Digital correlated double sampling circuit for sampling the outp

Facsimile and static presentation processing – Facsimile – Recording apparatus

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35821326, 358167, 35821318, H04N 514, H04N 5335, H04N 5213

Patent

active

050863444

ABSTRACT:
A digital correlated double sampling circuit employs three registers and a single clock signal to sample the output of a charge transfer device. The first register samples the reset reference value on the falling edge of the master clock cycle while the remaining two registers sample on the rising edge. The second register samples the image level and the third register samples the output of the first register, thus effecting a delay of the reset reference level. The outputs of the second and third registers, that is, the image level and the reset reference level, are differenced to provide a noise-free image signal.

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