Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-06-07

2005-06-07

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S200000

Reexamination Certificate

active

06903973

ABSTRACT:
A semiconductor memory device capable of accurately simulating a read-out timing of a memory cell and enhancing a production yield is provided. A dummy column selector is placed so as to be connected to dummy bit lines, and a plurality of dummy cells driving the dummy bit lines are placed at positions farthest in a column direction on a memory array from the side where an amplifier circuit is placed. This configuration allows a timing for driving the bit lines by the memory cells that are placed similarly at positions farthest from the amplifier circuit to be simulated accurately, thus enabling the generation of an amplifier startup signal without delay. Furthermore, a plurality of dummy word lines respectively connected to the plurality of dummy columns allow for readily switching from a dummy cell with a defect to a normal dummy cell.

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Osada, et al., “Universal-Vdd0.65-2.0-V 32-kB Cache Using a Voltage-Adapted Timing-Generation Scheme and a Lithographically Symmetrical Cell”, IEEE Journal of Solid-State Circuits, vol. 36, No. 11, Nov., 2001, pp. 1738-1744.

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