Memory device layout

Details Memory device layout Memory device layout

2005-12-13

2005-12-13

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S064000, C365S230030

Reexamination Certificate

active

06975527

ABSTRACT:
A number of memory array units are placed on a die. Each memory array within a unit is coupled to a channel that includes one or more data lines coupled to a pad on the die. Each memory array unit utilizes a different channel. Memory array units are grouped together in pairs on the die to form memory array groups. The two channels of each memory array group form boundaries on the die. The pads coupled to each channel of a memory array group are positioned within those boundaries. The pads may be arranged such that the same pad layout can be used across different dies fabricated for use at different bus widths. In one embodiment, a set of the pads are used in applications where the die is configured for a first bus width and a portion of the pads used in the first bus width applications are not used in applications where the die is configured to for a second bus width. By providing additional pads, the die may be connected to external leads in different bus width configurations and with different external lead sequences without substantially increasing the length of the internal data bus.

REFERENCES:
patent: 4393392 (1983-07-01), Hale
patent: 5097313 (1992-03-01), Fujii
patent: 5276893 (1994-01-01), Savaria
patent: 5453583 (1995-09-01), Rostoker et al.
patent: 5567655 (1996-10-01), Rostoker et al.
patent: 5604710 (1997-02-01), Tomishima et al.
patent: 5625603 (1997-04-01), McClure et al.
patent: 5744870 (1998-04-01), Casper
patent: 5825083 (1998-10-01), Takata et al.
patent: 5838627 (1998-11-01), Tomishima et al.
patent: 6057169 (2000-05-01), Singh et al.
patent: 6084300 (2000-07-01), Oka
patent: 6091089 (2000-07-01), Hiraga
patent: 6204689 (2001-03-01), Percey et al.
patent: 6211695 (2001-04-01), Agrawal et al.
patent: 6469327 (2002-10-01), Yasuda et al.
patent: 6628001 (2003-09-01), Chittipeddi et al.
patent: 2001/0000631 (2001-05-01), Zandman et al.
patent: 2001/0039644 (2001-11-01), Le Coz
patent: 2002/0004932 (2002-01-01), Shau
patent: 2002/0110942 (2002-08-01), Moghe et al.
patent: 2003/0031058 (2003-02-01), Kajigaya et al.
patent: 2003/0081443 (2003-05-01), Suwa et al.
patent: 2003/0090879 (2003-05-01), Doblar et al.
patent: 2003/0107123 (2003-06-01), Roohparvar
patent: 2003/0201528 (2003-10-01), Hsu

Affiliated with

Also associated with

Rating

Memory device layout does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device layout, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device layout will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3499556