Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2005-02-22
2005-02-22
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000
Reexamination Certificate
active
06859379
ABSTRACT:
The present invention provides a semiconductor memory device and memory system comprising a first semiconductor memory having a first peripheral circuit for transmitting and receiving memory data to/from a first memory cell array, a second semiconductor memory having a second peripheral circuit for transmitting and receiving the memory data to/from a second memory cell array, and a part of the peripheral circuit of the first semiconductor memory formed adjacent to the second memory cell array by a design rule of the second peripheral circuit.
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Kabushiki Kaisha Toshiba
Le Vu A.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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