Patent
1995-02-10
1998-01-27
Heckler, Thomas M.
395559, G06F 938
Patent
active
057130051
ABSTRACT:
A method and apparatus for pipelining data is used in a synchronous integrated memory circuit in which a read cycle is initiated by a first clock received on a clock input. The data associated with the read cycle propagates asynchronously through the memory to produce data which is then input to the pipeline circuit. The apparatus includes steering circuitry with precise timing for steering the data produced in the read cycle into an asserted one of several branches of a register. Selection circuitry is used to select for output the data which has been stored in the asserted branch upon receipt of a subsequent clock. The subsequent clock is one which occurs a programmable number of clocks after the first clock.
REFERENCES:
Choi, et al., "16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate," IEEE J. Solid-State Circuits 29:529-533 (1994).
L.W. Cotten, "Maximum-rate pipeline systems", Spring Joint Computer Conference, pp. 581-586 (May 14-16, 1969).
Wong et al., "Inserting Active Delay Elements to Achieve Wave Pipelining", IEEE Computer Society Press, pp. 270-273 (1989).
Jong et al., "Single Polysilicon Layer Advanced Super High-Speed BiCMOS Technology", IEEE, pp. 182-185 (1989).
Wong et al., "Designing High-Performance Digital Circuits Using Wave Pipelining", IFIP, 241-252 (1990).
Wong et al., "Techniques for Designing High-Performance Digital Circuits Using Wave Pipelining", A Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University, pp. ii-xvii and pp. 1-189 (Aug., 1991).
Wong et al., "A Bipolar Population Counter Using Wave Pipelining to Achieve 2.5x Normal Clock Frequency", IEEE, pp. 56-57 and 242 (1992).
Takai et al., "250Mbyte/sec Synchronous DRAM Using a 3-Stage-Pipelined Architecture", 1993 Symposium on VLSI Circuits; Digest of Technical Papers, (May 19-21, 1993).
Burleson, W., et al., "Wave-Pipelining: Is It Practical?", IEEE Proc, ISCAS '94, pp. 163-166, Jun., 1994.
Fujiwara, A., et al., "A 200MHz 16Mbit Synchronous DRAM with Block Access Mode," 1994 Symp. on VLSI Circuits, Digest of Technical Papers, pp. 79-80, May 1994.
Heckler Thomas M.
Townsend and Townsend and Crew LLP
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