Memory with low and fixed pre-charge loading

Details Memory with low and fixed pre-charge loading Memory with low and fixed pre-charge loading

2005-12-27

2005-12-27

Mai, Son (Department: 2827)

Static information storage and retrieval

Read only systems

Semiconductive

C365S094000, C257S390000

Reexamination Certificate

active

06980456

ABSTRACT:
A virtual ground memory with low and fixed pre-charge loading is provided. First metal lines GL(n−1), GL(n), and GL(n+1) and second metal lines BL(n−1) and BL(n) are disposed in the sequence GL(n−1), BL(n−1), GL(n), BL(n) and GL(n+1). Each first metal line and the adjacent second metal line are coupled respectively to two ends of the corresponding memory cell. Word lines are used for controlling memory cells. The second metal lines BL are in high level when the memory cells which the second metal lines BL are coupled to are chosen. A first and second sense amplifier are coupled to the second metal line BL(n−1) and BL(n) respectively, and the first metal lines GL(n−1) and GL(n+1) are coupled to ground level. One of the word lines is enabled to read the corresponding memory cells. A virtual ground memory loading can be fixed by this invention.

REFERENCES:
patent: 5650959 (1997-07-01), Hayashi et al.
patent: 5663903 (1997-09-01), Guo
patent: 5812440 (1998-09-01), Suminaga et al.
patent: 5825683 (1998-10-01), Chang
patent: 5875128 (1999-02-01), Ishizuka
patent: 6084794 (2000-07-01), Lu et al.

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