Method and apparatus for passing a bus clock signal from a compu

Details Method and apparatus for passing a bus clock signal from a compu Method and apparatus for passing a bus clock signal from a compu

1995-10-31

1997-04-22

Heckler, Thomas M.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Converting, per se, of an ac input to corresponding dc at an...

327165, G06F 110

Patent

active

056236492

ABSTRACT:
A computer (10) is coupled to an expansion chassis (12) containing one or more bus devices (18). A bus clock signal is passed to the expansion chassis (12) through connector (14). The bus clock signal received by the expansion chassis may be skewed from the original clock signal, due to conditioning to reduce EMI, or other filters. A clock regeneration circuit (20) produces a new clock signal for the bus devices which is in phase with the clock signal generated in the computer (10).

REFERENCES:
patent: 4208724 (1980-06-01), Rattingourd
patent: 4490821 (1984-12-01), Lacher
patent: 5359727 (1994-10-01), Kurita et al.
CGS701V Commercial Low Skew PLL 1 to 8 CMOS Clock Driver Data Sheet, National Semiconductor Corporation, (Aug. 1994).
Optimizing for Low Skew and Phase Error on PLL Based Clock Generators, Application Note 968, Rahim Ahmed and Louis Malarsie, National Semiconductor (Dec. 1994).

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