Sublithographic nanoscale memory architecture

Details Sublithographic nanoscale memory architecture Sublithographic nanoscale memory architecture

2005-11-08

2005-11-08

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

C257SE51040, C257SE51023, C977S726000

Reexamination Certificate

active

06963077

ABSTRACT:
A memory array comprising nanoscale wires is disclosed. The nanoscale wires are addressed by means of controllable regions axially and/or radially distributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires and microscale wires. In a two-dimensional embodiment, memory locations are defined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires located in different vertical layers.

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