Controlling processing clock signals

Details Controlling processing clock signals Controlling processing clock signals

1995-09-12

1997-04-22

Heckler, Thomas M.

G06F 110

Patent

active

056236468

ABSTRACT:
A data processing system is provided in which the central processing unit clock signal (mclk, fclk) to a central processing unit core (14) may be suspended to reduce power consumption. This suspension is controlled by a suspend controller (20) that responds to a write request to a predetermined address (0x0320001C) to hold asserted a bus request signal (REQ) that cooperates with a bus controller (18) to block the central processing unit clock signal. The central processing unit core sees the suspend mode as a write request of an indefinite length. The suspend controller is responsive to an asynchronous input signal (FIQ, IRQ, EVENT1) to exit the suspend mode by issuing a bus acknowledge signal (ACK) and removing the block on the central processing unit clock signal.

REFERENCES:
patent: 4851987 (1989-07-01), Day
patent: 5392437 (1995-02-01), Matter et al.
patent: 5471625 (1995-11-01), Mussemann et al.
patent: 5546568 (1996-08-01), Bland et al.

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