Semiconductor memory and method of driving the same

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185220, C365S185180

Reexamination Certificate

active

06856552

ABSTRACT:
Immediately after data write, a negative voltage which has an absolute value lager than that in data erase and which falls within a range over which no FN current flows is applied to a control gate, and at the same time 0 V is applied to a silicon substrate, source, and drain. In this manner, electrons trapped in a first gate oxide film are detrapped into the silicon substrate. This prevents a memory cell from passing write verify although electrons stored in a nitride film are few, prevents data changes caused by a decrease in the read margin, and improves the data holding characteristic of a memory cell.

REFERENCES:
patent: 5930173 (1999-07-01), Sekiguchi
patent: 5949717 (1999-09-01), Ho et al.

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