Flash memory device with distributed coupling between array...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185050, C365S185270

Reexamination Certificate

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06903970

ABSTRACT:
A flash memory device is disclosed in which includes a plurality of flash memory transistors disposed within a doped well. The transistors are coupled at respective sources to an array ground node via a plurality of array ground lines. A plurality of switching devices distributed throughout the doped well switchingly couple the array ground lines to the doped well to reduce an elevated voltage otherwise present on the array ground lines when the array ground lines are heavily loaded.

REFERENCES:
patent: 5646886 (1997-07-01), Brahmbhatt
patent: 6525969 (2003-02-01), Kurihara et al.
patent: 6717853 (2004-04-01), Abedifard et al.

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