Demodulators – Frequency modulation demodulator
Patent
1991-06-05
1992-08-11
Mis, David
Demodulators
Frequency modulation demodulator
329318, 329327, H03D 300
Patent
active
051382733
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relate to an FM demodulator used in, e.g, a VTR (Video Tape Recorder) and, more particularly, to an FM demodulator used for demodulating a reproduction signal.
BACKGROUND ART
FIG. 5 shows a conventional FM demodulator.
An FM signal reproduced by a reproduction head of a VTR (not shown) and converted into a square wave by a limiter circuit is supplied to an input terminal 11, and an FM signal having a phase opposite to that of the FM signal input to the input terminal 11 is supplied to an input terminal 12.
A first differential amplifier DA1 includes transistors Q1 and Q2. The base of the transistor Q1 is connected to the input terminal 11. The collector of the transistor Q1 is connected to the positive terminal of a power source V.sub.CC, and the emitter of the transistor Q1 is connected together with the emitter of the transistor Q2 to the negative terminal of the power source V.sub.CC through a first constant current circuit 13. The collector of the transistor Q2 is connected to the positive terminal of the power source V.sub.CC, and the base of the transistor Q2 is connected to the positive terminal of a power source V.sub.BB and the base of a transistor Q3. The negative terminal of the power source V.sub.BB is connected to the negative terminal of the power source V.sub.CC.
A differential amplifier DA2 includes the transistor Q3 and a transistor Q4. The collector of the transistor Q3 is connected together with the emitter of the transistor Q4 to the positive terminal of the power source V.sub.CC, and the emitter of the transistor Q3 is connected to the negative terminal of the power source V.sub.CC through a second constant current circuit 14. A current value I.sub.2 of the second constant current circuit 14 is set to be equal to a current value I.sub.1 of the first constant current circuit 13. In addition, a capacitor C is connected between the emitters of the transistors Q1 and Q2 and the emitters of the transistors Q3 and Q4.
The base of the transistor Q4 is connected to 1 input terminal 12, and the collector of the transistor Q4 is connected to the positive terminal of the power source V.sub.CC through a resistor R and to the non-inverting input terminal of a voltage comparator 15. The non-inverting input terminal of the voltage comparator 15 is connected to the negative terminal of the power source V.sub.CC through a reference power source Vref, and the output terminal of the voltage comparator 15 is connected to an output terminal through a low-pass filter LPF. The reference power source Vref is set by the following equation:
An operation of the demodulator with the above arrangement will be described below with reference to FIG. 6.
An FM signal indicated by reference symbol V.sub.A in FIG. 6 is supplied to the input terminal 11, and an FM signal indicated by reference symbol V.sub.B in FIG. 6 and having a phase opposite to that of the FM signal V.sub.A is supplied to the input terminal 12.
When the transistor Q1 is turned on at the leading edge of the FM signal VA indicated by 1 in FIG. 6, a collector current (I.sub.A =2I.sub.1) of the transistor Q1 flows through the first constant current circuit 13, the capacitor C, and the second constant current circuit 14. When a voltage V.sub.E becomes a voltage indicated by 2 in FIG. 6, the transistor Q3 is turned on, collector currents (I.sub.C =I.sub.1 =I.sub.2 and I.sub.A =I.sub.1) of the transistors Q3 and Q1 flow through the second and first constant current circuits 14 and 13, respectively.
When a opposite-phase FM signal V.sub.B rises as indicated by 3 and the transistor Q4 is turned on, a collector current (I.sub.D =2I.sub.1) of the transistor Q4 flows through the second constant current circuit 14, the capacitor C, and the first constant current circuit 13. When a voltage V.sub.D of the capacitor C becomes a voltage indicated by r in FIG. 6, the transistor Q2 is turned on, and the collector currents (I.sub.B =I.sub.1 and I.sub.D =I.sub.1) of the transistors Q2 and Q4 flow through the first and second cons
REFERENCES:
patent: 3783398 (1974-01-01), Dann
patent: 4843339 (1989-06-01), Burt et al.
Kabushiki Kaisha Toshiba
Mis David
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