Method of inlining a VHDL function call into Verilog

Details Method of inlining a VHDL function call into Verilog Method of inlining a VHDL function call into Verilog

2005-10-18

2005-10-18

Dam, Tuan (Department: 2192)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C717S106000

Reexamination Certificate

active

06957423

ABSTRACT:
A method of inlining a function call of a first high level design language (HDL) into a second HDL is disclosed comprising the steps of: (a) translating the function call of the first HDL into a function body file of the second HDL; (b) translating a signature of the function call of the first HDL into a data file including predetermined data of the function signature; and (c) translating the function call of the first HDL into a sequence of macro definitions based on the corresponding data file followed by a compiler directive to include the corresponding function body file of the second HDL. In one embodiment, the first HDL is a VHDL and the second HDL is a Verilog HDL.

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