Timing vernier using a delay locked loop

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input

Reexamination Certificate

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C327S244000

Reexamination Certificate

active

06853231

ABSTRACT:
A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the vernier being programmable to one of a plurality of timing steps within a delay range and the delay range being determined by a control signal applied to a bias input, the method comprising the steps of selecting a first and second control vernier from the plurality of verniers; programming the first control vernier to a first delay; programming the second control vernier to a second delay; triggering the first and second control verniers together to generate respective first and second delay signals; generating a difference pulse signal having a duty cycle corresponding to a difference between the generated first delay signal and second delay signal; comparing the duty cycle of the pulse signal to a duty cycle of the reference pulse signal to generate a difference signal pulse, the difference signal being coupled to the bias input of the verniers to adjust the delay range such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal. In a preferred embodiment there is provided a circuit for implementing the method.

REFERENCES:
patent: 6052011 (2000-04-01), Dasgupta
patent: 6121826 (2000-09-01), Dosho et al.
patent: 6680635 (2004-01-01), Lee

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