Address decoder array composed of CMOS

Details Address decoder array composed of CMOS Address decoder array composed of CMOS

1991-05-22

1992-08-11

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3073032, 357 42, 357 45, H03K 1920, H01L 2500

Patent

active

051381974

ABSTRACT:
A NAND-system address decoder is configured by arranging the P-channel- and N-channel logical blocks in parallel and input wires to which address signals are supplied is extendedy formed in the direction in which the above logical blocks are arranged. And, output lines extended from each logical block are connected to a output portion in parallel. The P-channel- and N-channel logical circuits are configured by collection of local decode circuits. The local decode circuit is composed of a P-channel MISFET circuit consisting of parallely-connected P-channel MISFETs corresponding to the number of address-signal bits and a N-channel MISFET circuit consisting of serially-connected N-channel MISFETs corresponding to the number of address-signal bits. The MISFET configuring each MISFET circuits are configured so that a gate will be set at the position to which the above input wires will extend.

REFERENCES:
patent: 4949157 (1990-08-01), Minami
patent: 4965651 (1990-10-01), Wagner
patent: 4992845 (1991-02-01), Arakawa et al.

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