Boots – shoes – and leggings
Patent
1994-10-31
1997-04-22
Lee, Thomas C.
Boots, shoes, and leggings
395285, 395306, 395290, 395180, 364228, 364240, 3642411, G06F 1200, G06F 1202, G06F 1338
Patent
active
056236107
ABSTRACT:
Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support an hierarchical view of the serial bus elements, logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.
REFERENCES:
patent: 3245045 (1966-04-01), Randlev
patent: 3916387 (1975-10-01), Woodrum
patent: 3932841 (1976-01-01), Deerfield et al.
patent: 4070704 (1978-01-01), Calle et al.
patent: 4092491 (1978-05-01), Frazer
patent: 4409656 (1983-10-01), Andersen et al.
patent: 4606052 (1986-08-01), Hirzel et al.
patent: 4660141 (1987-04-01), Ceccon et al.
patent: 4689740 (1987-08-01), Moelands et al.
patent: 4713834 (1987-12-01), Brahm et al.
patent: 4748346 (1988-05-01), Emori
patent: 4870704 (1989-09-01), Matelan et al.
patent: 4885742 (1989-12-01), Yano
patent: 4912633 (1990-03-01), Schweizer et al.
patent: 4914650 (1990-04-01), Sriram
patent: 4984190 (1991-01-01), Katori et al.
patent: 5001707 (1991-03-01), Kositpaiboon
patent: 5063574 (1991-11-01), Moose
patent: 5130983 (1992-07-01), Heffner, III
patent: 5173939 (1992-12-01), Abadi et al.
patent: 5179670 (1993-01-01), Farmwald et al.
patent: 5237690 (1993-08-01), Bealkowski et al.
patent: 5257160 (1993-10-01), Yokohama et al.
patent: 5269011 (1993-12-01), Yanai et al.
patent: 5282202 (1994-01-01), Bernstein et al.
patent: 5317597 (1994-05-01), Eisele
patent: 5341131 (1994-08-01), Hoshini et al.
patent: 5341480 (1994-08-01), Wasseman et al.
patent: 5361261 (1994-11-01), Edem et al.
patent: 5379384 (1995-01-01), Solomon
patent: 5386567 (1995-01-01), Lien et al.
patent: 5394556 (1995-02-01), Oprescu
patent: 5418478 (1995-05-01), Van Brunt et al.
patent: 5440181 (1995-08-01), Gruender, Jr. et al.
patent: 5440556 (1995-08-01), Edem et al.
patent: 5446765 (1995-08-01), Leger
patent: 5463620 (1995-10-01), Sriram
patent: 5463624 (1995-10-01), Hogg et al.
patent: 5483518 (1996-01-01), Whetsel
patent: 5542055 (1996-07-01), Amini et al.
Dean McCarron, Pulg-and Play Specification Introduced: Microsoft, Intel, Others Annouce User-Friendly ISA BUS, 7 Microprocessor Report 224 May 1993.
GLOBECOM'92: IEEE Global Telecommunications Conference; Sriram "Methodologies For Bandwidth Allocation, Transmission Scheduling, And Congestion Avoidance In Broadband ATM".
GLOBECOM'90: IEEE Global Telecommunications Conference; Aicardi, et al. "Adaptive Bandwidth Assignments In A TDM Network With Hybrid Frames", pp. 41-42.
Local Computer Networks, 1991 16th Conference, Issued 13 Mar. 1991, R. Bolla et al, "A traffic control strategy for a DQDB-type MAN", pp. 195-196.
Wireless Communications, Selected Topics, Int'l. conference 1992, Issued Feb. 1992, K. S. Natarajan, "A hybrid medium access Protocol for Wireless LANS", pp. 134-136.
IEEE Transactions on Communications, Z. Zhang et al, "Bounds on the mean system-size and Delay for a movable-boundary integrated circuit and packet switched communications".
GLOBECOM'92: IEEE Global Telecommunications Conference; Bolla et al. "A Neutral Strategy For Optimal Multiplexing Of Circuit-And Packet-Switched Traffic." 1992 pgs.
Philips' I C (Inter-Integrated Circuit) Bus, 5 pages.
Concentration Highway Interface (CHI), AT&T Microelectronics Interface Specification, Nov. 1990 (DS90-124SMOS).
ATA/ANSI 878.1, Version 1.9 (59 Sheets), Copyright 1992 ARCNET Trade Association.
PCMCIA PC Card Standard, Release 2.01, 1.1-4.8.9, Copyright 1992 PCMCIA.
ACCESS.bus.TM. Specifications--Version 2.2.
High Performance Serial Bus, P1394/Draft 6.2v0, Copyright 1993 IEEE.
Bhatt Ajay V.
Cadambi Sudarshan B.
Callahan Shelagh
Knoll Shaun
Morriss Jeff C.
Chen Anderson I.
Intel Corporation
Lee Thomas C.
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