Method and apparatus for implementing signed multiplication...

Details Method and apparatus for implementing signed multiplication... Method and apparatus for implementing signed multiplication...

2005-12-06

2005-12-06

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S628000, C708S629000

Reexamination Certificate

active

06973471

ABSTRACT:
A multiplier (42) forms a product from two signed operands without performing a sign extension of the multiplicand (A). A modified Booth's recoding of the multiplier operand (B) is begun immediately without being delayed by a sign extension operation. While recoding and partial product generation is occurring, a determination is made in parallel whether or not a sign extension adjustment term must be created. When needed, a value equal to (−B) (2N), where N is equal to a bit width of the multiplicand (A), is formed in parallel with the recoding and partial product generation. The sign extension adjustment term is coupled to a plurality of carry save adders (49, 51, 53) that compress a plurality of partial products to a sum term and a carry term. A final add stage combines the sum term and carry term to provide a product with correct sign extension.

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patent: 2003/0005016 (2003-01-01), Tzeng et al.

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