Semiconductor memory device for differential data...

Details Semiconductor memory device for differential data... Semiconductor memory device for differential data...

2005-12-13

2005-12-13

Mai, Son (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S210130

Reexamination Certificate

active

06975540

ABSTRACT:
It is intended to provide a semiconductor memory device capable of making margin of readout operation constant regardless of any selected memory cells wherein the number of reference cells is restrained to minimum essential number and reference current value of which depends on a selected memory cell is obtained. A memory cell selected by address Y(X) is connected to a data line DB and data in the memory cell is read out from a memory cell array3.Then, a differential amplifier4amplifies the data with reference to a reference value supplied to a reference line RB from a reference section2.The reference section2is constituted by a reference cell RC and a source resistance adjustor section1that is connected to a source terminal of the reference cell RC. A load adjustor section1adjusts a resistance value that is connected to the source terminal of the reference cell RC by the address Y(X). A source resistance adjustor section1connects a load equivalent to a load selected by a memory cell in accordance with the address Y(X) to the reference cell RC, whereby an appropriate reference value is constantly supplied.

REFERENCES:
patent: 5091888 (1992-02-01), Akaogi
patent: 6370060 (2002-04-01), Takata et al.
patent: 6754106 (2004-06-01), Wu et al.
patent: 4-67500 (1992-03-01), None

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