High performance vias for vertical IC packaging

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S687000, C257S688000, C257S689000, C438S109000

Reexamination Certificate

active

06936913

ABSTRACT:
A semiconductor device, a microelectromechanical system package and a method of making the same utilize high performance vias for vertical IC packaging. A semiconductor die of the device/package has a substrate with integrated circuitry formed on a front side of the substrate. A metal bonding pad overlies the substrate on the front side of the substrate and is electrically connected to the integrated circuitry. A solder bump is located on the metal bonding pad. An electrically conductive via extends through the substrate from the metal bonding pad to a back side of the substrate where the via forms a side wall of a via hole. A plurality of the substrates are stacked on one another with the outer end of the solder bump of one substrate fitting within the via hole of an adjacent substrate. During reflow soldering, surface tension forces of the molten solder bump self-align the substrates.

REFERENCES:
patent: 3761782 (1973-09-01), Youmans
patent: 4807021 (1989-02-01), Okumura
patent: 5229647 (1993-07-01), Gnadinger
patent: 6219254 (2001-04-01), Akerling et al.
patent: 6667551 (2003-12-01), Hanaoka et al.
patent: 6674161 (2004-01-01), Haba
patent: 2002/0017710 (2002-02-01), Kurashima et al.
patent: WO 96/13062 (1996-05-01), None
S. Linder, et al.; Fabrication Technology for Wafer Through-Hole Interconnections and Three-Dimensional Stacks of Chips and Wafers ; Jan. 25, 1994; pp. 349-354.
European Search Report mailed Nov. 28, 2003 in European application No. 03017796.8-2203.
RDA, “RD Automation CDB-50 Flip Chip Die Bonder,” website ad, p. 3, (Dec. 10, 2001).
Jordan Neysmith and Daniel F. Baldwin, “A Modular, Chip Scale, Direct Chip Attach MEMS Package: Architecture and Processing,” The International Journal of Microcircuits and Electronic Packaging, vol. 23 (No. 4), p. 474-480, (Dec. 10, 2000).

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