Semiconductor memory with address decoding unit, and address...

Details Semiconductor memory with address decoding unit, and address... Semiconductor memory with address decoding unit, and address...

2005-08-30

2005-08-30

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S230020

Reexamination Certificate

active

06937537

ABSTRACT:
A semiconductor memory includes: at least two memory banks that each have a memory cell matrix, an address decoding unit which includes a bank address decoding unit, a row address decoding unit and a column address decoding unit. At least one demultiplexer is connected upstream of the address buffer memories provided in the row address decoding unit and/or in the column address decoding unit. This demultiplexer is connected to the bank address decoder in order, on the basis of the decoded bank address, to activate the corresponding address buffer memory.

REFERENCES:
patent: 5986965 (1999-11-01), Lee
patent: 6205076 (2001-03-01), Wakayama et al.
patent: 2002/0054518 (2002-05-01), Ooishi et al.

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