Method and apparatus for subclocking a SAR analog-to-digital...

Details Method and apparatus for subclocking a SAR analog-to-digital... Method and apparatus for subclocking a SAR analog-to-digital...

2005-10-18

2005-10-18

Jeanglaude, Jean (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06956518

ABSTRACT:
Method and apparatus for subclocking a SAR analog-to-digital converter. A method is disclosed for clocking the operation of a SAR analog-to-digital converter (ADC). A low frequency clock and a high frequency clock are provided. An analog input voltage is then tracked during a tracking phase to sample the value thereof. A conversion cycle referenced to an edge of the low frequency clock is then initiated. The sampled data is then converted in a conversion operation during a data conversion cycle, which conversion operation requires a plurality of conversion clock cycles, the timing of at least a portion of the conversion operation is controlled during the data conversion cycle utilizing the high frequency clock as the conversion clock.

REFERENCES:
patent: 4620179 (1986-10-01), Cooper et al.
patent: 4851838 (1989-07-01), Shier
patent: 6181269 (2001-01-01), Nishiuchi et al.
patent: 6232905 (2001-05-01), Smith et al.
patent: 6664908 (2003-12-01), Sundquist et al.
patent: 6771202 (2004-08-01), Watanabe et al.

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