Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

2005-02-15

2005-02-15

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185300, C365S185290

Reexamination Certificate

active

06856548

ABSTRACT:
A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1and is lower than OEVT. The erase verify threshold values EVT1and EVT2are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.

REFERENCES:
patent: 5237535 (1993-08-01), Mielke et al.
patent: 5568419 (1996-10-01), Atsumi et al.
patent: 5859799 (1999-01-01), Matsumoto et al.
patent: 5926430 (1999-07-01), Noda et al.
patent: 6002630 (1999-12-01), Chuang et al.
patent: 6038165 (2000-03-01), Miwa et al.
patent: 6108263 (2000-08-01), Bauser et al.
patent: 6122193 (2000-09-01), Shibata et al.
patent: 6172917 (2001-01-01), Kataoka et al.
patent: 6236609 (2001-05-01), Tanzawa et al.
patent: 6246625 (2001-06-01), Yamagata et al.
patent: 6278316 (2001-08-01), Tanzawa et al.
patent: 6292399 (2001-09-01), Le et al.
patent: 6314027 (2001-11-01), Choi
patent: 6331945 (2001-12-01), Shibata et al.
patent: 6373748 (2002-04-01), Ikehashi et al.
patent: 6418052 (2002-07-01), Shibata et al.
patent: 6442080 (2002-08-01), Tanzawa et al.
patent: 6483752 (2002-11-01), Hirano
patent: 6515908 (2003-02-01), Miyawaki et al.
patent: 6567316 (2003-05-01), Ohba et al.
patent: 6714459 (2004-03-01), Hirano
patent: 20010050377 (2001-12-01), Ikehashi et al.
patent: 20020008996 (2002-01-01), Hirano
patent: 20020141237 (2002-10-01), Goda et al.
patent: 20020181292 (2002-12-01), Tanzawa et al.
S. Yamada et al., “A Self-Convergence Erasing Scheme For A Simple Stacked Gate Flash EEPROM”, pp. 11.4.1-11.4.4.
H. Shiga et al., “A Sampling Weak-Program Method to Tighten Vth-distribution of 0.5V for Low-Voltage Flash Memories”, 1995, pp. 33-36.

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