Pattern layout of transfer transistors employed in row decoder

Details Pattern layout of transfer transistors employed in row decoder Pattern layout of transfer transistors employed in row decoder

2005-12-06

2005-12-06

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S063000, C365S230060

Reexamination Certificate

active

06972996

ABSTRACT:
A semiconductor device comprises a memory cell array and a word-line select circuit. The memory cell array includes a plurality of memory cells arranged in rows and columns. The memory cell array includes a plurality of blocks in each one of which the memory cells are arranged. The word-line select circuit includes transfer transistors arranged in row and column directions, and is configured to transfer a plurality of different voltages to word lines through current paths of the transfer transistors and select memory cells of at least one row of said plurality of blocks. The transfer transistors include a first group, which transfers the lowest voltage of voltages applied to the word lines in a writing operation and a second group, which is arranged not to be adjacent to the first group and transfers the highest voltage of voltages applied to the word lines in a writing operation.

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