Coating processes – Direct application of electrical – magnetic – wave – or... – Pretreatment of substrate or post-treatment of coated substrate
Reexamination Certificate
2005-02-08
2005-02-08
Padgett, Marianne (Department: 1762)
Coating processes
Direct application of electrical, magnetic, wave, or...
Pretreatment of substrate or post-treatment of coated substrate
C427S559000, C427S553000, C438S473000, C438S476000
Reexamination Certificate
active
06852371
ABSTRACT:
A method is provided for gettering impurities from silicon wafers and devices to improve the quality of the material and the device performance. The wafer or the device is coated on the back-side with a layer of aluminum and is illuminated form the other side with light having a significant portion of energy in the IR region. This process leads to formation of a Si—Al melt on the backside, at temperature below 550° C. Dissolved impurities in the Si diffuse toward the Al melt and are trapped there. At higher illuminations and concomitant higher temperatures, the Al interface serves as a source of point defect injection. This mode of processing causes dissolution of precipitated impurities at greatly reduced temperatures and in short periods of time.
REFERENCES:
patent: 4311870 (1982-01-01), Frosch et al.
patent: 4994399 (1991-02-01), Aoki
patent: 5223453 (1993-06-01), Sopori
patent: 5304509 (1994-04-01), Sopori
patent: 5426061 (1995-06-01), Sopori
patent: 5627081 (1997-05-01), Tsuo et al.
patent: 5897331 (1999-04-01), Sopori
patent: 6043137 (2000-03-01), Krueger et al.
patent: 6201261 (2001-03-01), Sopori
patent: 6228748 (2001-05-01), Anderson et al.
patent: 6465288 (2002-10-01), Ohnuma
patent: 20020106841 (2002-08-01), Yamazaki
patent: 20040102056 (2004-05-01), Tobe et al.
patent: 20040115906 (2004-06-01), Makita et al.
patent: 59 087877 (1984-05-01), None
patent: 63 108729 (1988-05-01), None
Translation to JP 59-087877 to Ishikawa et al.*
JPO & Derwent abstracts to JP 359087877A (JP 59-87877) to Toshiba Corp, Ishikawa et al, May 21, 1984.*
JPO & Derwent English abstracts to JP363108729A (63-108729) to Nec Corp, Yamamoto et al, May 13, 1988.*
Translation to Yamamoto et al (JP 63-108729), May 13, 1988.*
Henquinet, N.G., et al., “Limiting Factors of Backside External Gettering by Nanocavities And Aluminum-Silicon Alloying in Silicon Wafers,” proceedings of the Materials Research Society Symposium, 1998, pp. 221-226, vol. 510, France, no month.
Midwest Research Institute
Padgett Marianne
White Paul J.
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