Semiconductor device having a wiring layer of damascene...

Details Semiconductor device having a wiring layer of damascene... Semiconductor device having a wiring layer of damascene...

2005-06-14

2005-06-14

Wilson, Allan R (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S410000, C257S522000, C257S386000, C257S397000, C257S305000, C257S283000, C257S244000, C257S311000, C257S210000, C257S374000, C257S513000, C257S520000, C257S575000, C257S508000, C257S750000, C257S774000, C257S330000, C257S332000

Reexamination Certificate

active

06906419

ABSTRACT:
In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

REFERENCES:
patent: 5677563 (1997-10-01), Cronin et al.
patent: 5963818 (1999-10-01), Kao et al.
patent: 6064107 (2000-05-01), Yeh et al.
Miyashita et al., “A Novell Bit-Line Process Using Poly-Si Masked Dual-Damascene (PMDD) for 0.13 μm DRAMs and Beyond”, IEDH Tech. 2000, pp. 361-362, Dec. 2000.

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