Method of reducing disturbs in non-volatile memory

Details Method of reducing disturbs in non-volatile memory Method of reducing disturbs in non-volatile memory

Filed on

2005-12-20

Date issued

2005-12-20

Examiner

Phung, Anh (Department: 2824)

Patent Class

Static information storage and retrieval

SubClass

Floating gate

SubSubClass

Particular biasing

Other Related Categories

C365S185120

Type

Reexamination Certificate

Status

active

Patent number

06977844

Description

ABSTRACT:
In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

REFERENCES:
patent: 5095344 (1992-03-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5396468 (1995-03-01), Harari et al.
patent: 5418752 (1995-05-01), Harari et al.
patent: 5532962 (1996-07-01), Auclair et al.
patent: 5598370 (1997-01-01), Niijima et al.
patent: 5172338 (1997-07-01), Mehrotra et al.
patent: 5663923 (1997-09-01), Baltar et al.
patent: 5818753 (1998-10-01), Gotou
patent: 5890192 (1999-03-01), Lee et al.
patent: 5995414 (1999-11-01), Sato
patent: 6069039 (2000-05-01), Lee et al.
patent: 6157983 (2000-12-01), Lee et al.
patent: 6236593 (2001-05-01), Hong et al.
patent: 6314025 (2001-11-01), Wong
patent: 6639842 (2003-10-01), Hoang et al.
patent: 2003/0051093 (2003-03-01), Takeuchi
patent: 0 459 633 (1991-04-01), None
patent: 0 899 744 (1999-03-01), None
Copy of PCT Search Report dated Jul. 9, 2003.

Affiliated with

Also associated with

Rating

Method of reducing disturbs in non-volatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of reducing disturbs in non-volatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing disturbs in non-volatile memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3473954