Electrostatic discharge clamp

Details Electrostatic discharge clamp Electrostatic discharge clamp

2005-08-09

2005-08-09

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06927957

ABSTRACT:
According to one exemplary embodiment, an ESD bus clamp in an integrated circuit comprises an inverter having an input and an output. The ESD bus clamp further comprises a bipolar transistor having a base, an emitter, and a collector, where the base is connected to the output of the inverter, the emitter is connected to a ground of the integrated circuit, and the collector is connected to a power bus of the integrated circuit. The bipolar transistor, for example, may be an NPN bipolar transistor and may begin shunting current to the ground when an ESD discharge causes a voltage level on the power bus to increase by approximately 1.0 volt. According to this exemplary embodiment, the ESD bus clamp further comprises a resistor coupling the input of the inverter to the power bus. The ESD bus clamp further comprises a capacitor coupling the input of the inverter to ground.

REFERENCES:
patent: 5440162 (1995-08-01), Worley et al.
patent: 5500546 (1996-03-01), Marum et al.
patent: 5654862 (1997-08-01), Worley et al.
patent: 5726844 (1998-03-01), Smith
patent: 5946177 (1999-08-01), Miller et al.
patent: 5978192 (1999-11-01), Young et al.
patent: 6400540 (2002-06-01), Chang
patent: 6455902 (2002-09-01), Voldman

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