Method for preventing electrostatic discharge failure in an inte

Details Method for preventing electrostatic discharge failure in an inte Method for preventing electrostatic discharge failure in an inte

1996-05-06

1998-01-27

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 361220, H02H 322

Patent

active

057127530

ABSTRACT:
An integrated circuit package includes a semiconductor chip, bonding pads on the semiconductor chip, a plurality of wired pins wire-bonded respectively to the bonding pads, and at least one non-wired pin. The non-wired pin is connected electrically to an adjacent one of the wired pins to prevent electrostatic discharge failure in the integrated circuit package due to electrostatic discharge stressing of the non-wired pin.

REFERENCES:
patent: 4819047 (1989-04-01), Gilfeather et al.
patent: 4870530 (1989-09-01), Hurst et al.
patent: 4878145 (1989-10-01), Lace
patent: 5012317 (1991-04-01), Rountre
patent: 5034845 (1991-07-01), Murakami
patent: 5159518 (1992-10-01), Roy
patent: 5515225 (1996-05-01), Gen et al.

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