Patent
1975-11-04
1977-05-03
Olms, Douglas W.
H04R 500
Patent
active
040216128
ABSTRACT:
This invention discloses a control circuit to be used in a decoder apparatus applicable to matrix 4-channel systems of different types. The control circuit is adapted to control, according to the type of composite signals to be decoded by the decoder apparatus, at least first and second gain control amplifiers which control the amplitude ratio between signals to be combined into output signals, and includes an FET array comprised of at least four field effect transistors formed in a semiconductor chip. First and second field effect transistors in the FET array are so connected to a DC power source that different predetermined DC currents may flow through their source-drain paths. To the first and second gain control amplifiers, third and fourth field effect transistors of the FET array are coupled respectively in such a manner that the internal resistances between their source-drain paths control the gains of the first and second amplifiers. The third and fourth field effect transistors are supplied with DC bias volates produced by either the first field effect transistor or the second field effect transistor, selectively in accordance with the type of the composite signals to be decoded.
REFERENCES:
patent: 3691298 (1972-09-01), Pittman et al.
patent: 3783192 (1974-01-01), Takahashi
patent: 3825684 (1974-07-01), Ito et al.
patent: 3836715 (1974-09-01), Ito et al.
patent: 3887770 (1975-06-01), Takahashi
patent: 3934086 (1976-01-01), Takahashi
Olms Douglas W.
Sansui Electric Co. Ltd.
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