Delay locked loop circuit with duty cycle correction function

Details Delay locked loop circuit with duty cycle correction function Delay locked loop circuit with duty cycle correction function

2005-11-08

2005-11-08

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S175000

Reexamination Certificate

active

06963235

ABSTRACT:
A delay locked loop (DLL) circuit having a structure in which a method of performing duty cycle correction (DCC) using two DLLs and an intermediate phase composer and a method of performing DCC by forming a closed loop using a negative feedback are combined with each other is provided. The DLL circuit includes a first DLL for receiving an external clock signal and generating a first clock signal and a second DLL for receiving an external clock signal and generating a second clock signal. The first clock signal and the second clock signal are synchronized with an external clock signal. The DLL circuit further includes an intermediate phase generation circuit for receiving the first and second clock signals and generating an intermediate phase clock signal and a DCC loop for receiving the intermediate phase clock signal and generating an output clock signal. The intermediate phase clock signal has an intermediate phase between the phases of the first and second clock signals. The output clock signal is generated through correction of the duty cycle of the intermediate phase clock signal using a value obtained by integrating the output clock signal.

REFERENCES:
patent: 6452432 (2002-09-01), Kim
patent: 6466071 (2002-10-01), Kim et al.
patent: 6573771 (2003-06-01), Lee et al.
patent: 6643787 (2003-11-01), Zerbe et al.
patent: 6677792 (2004-01-01), Kwak
patent: 6768361 (2004-07-01), Kwak
patent: 2003/0219088 (2003-11-01), Kwak

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