Semiconductor memory device having bit line kicker

Details Semiconductor memory device having bit line kicker Semiconductor memory device having bit line kicker

2005-06-14

2005-06-14

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230030, C365S203000, C365S230060, C365S230080, C365S189060

Reexamination Certificate

active

06906979

ABSTRACT:
A plurality of cell arrays is provided with a plurality of word lines and bit line pairs. A plurality of sense amplifiers is connected so as to each of the plurality of bit line pairs. The plurality of sense amplifiers configures a memory core section together with the plurality of cell arrays. A pair of bit line kicker drive lines is arranged in the vicinity of the plurality of cell arrays, and a pair of bit line kickers is connected between the pair of bit line kicker drive lines and each of the plurality of bit line pairs. In the memory core section, a pair of drivers is arranged so as to correspond to each cell array, and each of the pair of drivers has an output node connected to the pair of bit line kicker drive lines. The pair of drivers drives the pair of bit line kicker drive lines so as to change a potential of one bit line of one of the plurality of bit line pairs via the pair of bit line kickers.

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Lim, K., et al., “Bit Line Coupling Scheme and Electrical Fuse Circuit for Reliable Operation of High Density DRAM,”2001 Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2001.

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