Static information storage and retrieval – Addressing – Sync/clocking
Patent
1996-01-03
1997-04-22
Nelms, David C.
Static information storage and retrieval
Addressing
Sync/clocking
365193, 365227, 3652335, G11C 800
Patent
active
056234538
ABSTRACT:
A synchronous semiconductor device operates in synchronism with clock signal supplied from an external unit. The synchronous semiconductor device can be set in a first mode (a CSUS mode) and a power down mode (a PD mode) as an operation mode when a predetermined external signal (a CKE signal) is in a predetermined state. The synchronous semiconductor device includes a first signal generating circuit for generating a rasz signal which may be in a first state and in a second state which permits the synchronous semiconductor device to be in a state where data is not output, a second signal generating circuit for generating a rasdz signal, a change of the rasdz signal from a first state to a second state being delayed for a delay time from a change of the rasz signal generated by the first signal generating circuit from the first state to the second state, and a power down control circuit for activating the power down mode in synchronism with the clock signal when the rasdz signal is in the second state under a condition in which the predetermined external signal is in the predetermined state, so that the synchronous semiconductor device is in the power down mode.
REFERENCES:
patent: 4906862 (1990-03-01), Itano et al.
patent: 5113373 (1992-05-01), Lee
patent: 5473572 (1995-12-01), Margeson, III
Fujitsu Limited
Nelms David C.
Niranjan F.
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