Trench isolation for semiconductor devices

Details Trench isolation for semiconductor devices Trench isolation for semiconductor devices

2005-02-15

2005-02-15

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S292000, C257S306000, C257S398000, C257S413000

Reexamination Certificate

active

06856001

ABSTRACT:
A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are implanted into the substrate in regions directly below the isolation trench after partially filling the trench with the dielectric material. The dielectric along the sidewalls of the trenches can serve as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. The dielectric along the sidewalls of the trenches serves as a mask so that substantially all of the ions implanted below the isolation trenches are displaced from the active regions. After the ions are implanted in the substrate below the trenches, the remainder of the trench can be filled with the same or another dielectric material. The trench isolation technique can be used to fabricate memory, logic and imager devices which can exhibit reduced current leakage and/or reduced optical cross-talk.

REFERENCES:
patent: 3386865 (1968-06-01), Doo
patent: 3755001 (1973-08-01), Kool et al.
patent: 4443932 (1984-04-01), Mastroianni et al.
patent: 4799093 (1989-01-01), Kohara et al.
patent: 4990983 (1991-02-01), Custode et al.
patent: 5250450 (1993-10-01), Lee et al.
patent: 5397908 (1995-03-01), Dennison et al.
patent: 5433794 (1995-07-01), Fazan et al.
patent: 5492853 (1996-02-01), Jeng et al.
patent: 5693971 (1997-12-01), Gonzalez
patent: 5702976 (1997-12-01), Schuegraf et al.
patent: 5706164 (1998-01-01), Jeng
patent: 5841163 (1998-11-01), Joo et al.
patent: 5859451 (1999-01-01), Narita
S. Nag et al., “Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25 μm Technologies”, IEEE 1996, pp. 841-844.
S. Mendis et al., “Progress in CMOS Active Pixel Image Sensors”, SPIE vol. 2172, Feb. 1994, pp. 19-29.
S.B. Campana, “Techniques for Evaluating Charge Coupled Imagers”, Optical Engineering, May-Jun. 1977, vol. 16, No. 3, pp. 167-274.
S. Mendis et al., “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems”, IEEE 1997, pp. 187-197.
S. Mendis et al., “A 128 × 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems”, IEEE 1993, pp. 583-586.

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