Electrically-erasable ROM with pulse-driven memory cell transist

Static information storage and retrieval – Floating gate – Particular biasing

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36518525, G11C 1134

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active

056234449

ABSTRACT:
The drain of a memory cell transistor is connected to a sub bit line of an EEPROM. The sub bit line is connected to a main bit line via the drain-source path of a selection transistor. The equivalent capacitance of the sub bit line is precharged to the potential of the main bit line when the selection transistor is temporarily turned on. The potential of the precharged sub bit line tends to drop in the presence of a leakage current component equivalent resistance. However, when the selection transistor is intermittently turned on by using pulses to supply charges from the main bit line to the sub bit line, a drop in sub bit line potential can be prevented.

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