Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-02-01
2005-02-01
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S433000, C438S435000, C257S506000, C257S519000
Reexamination Certificate
active
06849519
ABSTRACT:
A method of forming an isolation layer in semiconductor devices is disclosed. The method includes forming the isolating film by means of a method in which a method of forming a V-type trench at the isolation region, implanting ions capable of accelerating oxidization action into the center portion of the V-type trench, implementing an oxidization process to form an insulating film consisting of an oxide film at the isolation region, and then completely burying the trench with an insulating material, using the LOCOS method, and a method of forming a trench type isolation layer, are applied together. Therefore, as the top corner of the trench is formed with an inclination, and a concentration of the electric field and a formation of a moat can be simultaneously prevented.
REFERENCES:
patent: 4866004 (1989-09-01), Fukushima
patent: 6165871 (2000-12-01), Lim et al.
patent: 6355540 (2002-03-01), Wu
Lee Calvin
Marshall & Gerstein & Borun LLP
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