Structure and method of using an arithmetic and logic unit for c

Details Structure and method of using an arithmetic and logic unit for c Structure and method of using an arithmetic and logic unit for c

1994-07-27

1997-04-22

Gordon, Paul P.

Boots, shoes, and leggings

364736, 364754, 364787, G06F 752, G06F 750

Patent

active

056234341

ABSTRACT:
A multiplier circuit for use in a system which includes an arithmetic and logic unit (ALU). The multiplier circuit includes a carry save stage which receives a first data value and a second data value, and in response, creates a carry signal and a sum signal. The carry and sum signals are provided to input leads of the ALU. The ALU is used to add the carry and sum signals to create a third data value which is equal to the product of the first and second data values. In one embodiment, the input leads to the ALU are multiplexed. Thus, one input lead of the ALU receives either the carry signal or a signal from a first input node and the second input lead of the ALU receives either the sum signal or a signal from a second input node.

REFERENCES:
patent: 5204828 (1993-04-01), Kohn
patent: 5227987 (1993-07-01), Imazawa et al.
patent: 5245564 (1993-09-01), Quek et al.
patent: 5299319 (1994-03-01), Vassiliadis et al.
patent: 5359718 (1994-10-01), Phillips et al.
patent: 5426743 (1995-06-01), Phillips et al.

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