Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Nonsignificant zero elimination
Reexamination Certificate
2005-06-07
2005-06-07
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Nonsignificant zero elimination
C377S006000, C377S016000, C377S049000
Reexamination Certificate
active
06904114
ABSTRACT:
A ones counter that accepts a binary input word of ones and zeros and provides a binary output word indicative of the number of ones within the input word. A two-dimensional array is built with a plurality of like cells connected in a regular manner with the first row of the array determining the least significant bit of the output word and each subsequent row determining the output word's next most significant bit. The first row of the array contains approximately one-half the number of cells as bits in the input word with each subsequent row of the array containing approximately one-half the number of cells of the preceding row with the final row containing a single cell that determines the most significant bit of the binary output word. The ones-count output word is computed asynchronously without clocking circuits or data storage elements.
REFERENCES:
patent: 3711692 (1973-01-01), Batcher
Cullers David Kent
Shackleford J. Barry
Shackleford J. Barry
Wambach Margaret R.
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