Stacked H-cell capacitor and process to fabricate same

Details Stacked H-cell capacitor and process to fabricate same Stacked H-cell capacitor and process to fabricate same

1991-05-10

1992-08-11

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437 60, 437228, H01L 21265, H01L 2170

Patent

active

051378426

ABSTRACT:
An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked H-Cell (SHC). The SHC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SHC is made up of a polysilicon storage node structure having a H-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SHC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an H-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.

REFERENCES:
patent: 4742018 (1988-05-01), Kimura et al.
patent: 5049957 (1991-09-01), Inoue et al.
patent: 5095364 (1992-03-01), Bae et al.
patent: 5108948 (1992-04-01), Sandhu et al.
"Crown-Shaped Stacked-Capacitor Cell for 1.5 V Operation 64-Mb DRAM's" by Toru Kaga, et al., pp. 255-261, 1991 IEEE.
"3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS" by T. Ema et al., pp. 592-595, IEDM 88, '91.
"A New Stacked Capacitor Cell With Thin Box Structured Storage Node" by S. Inoue, etal., pp. 141-144, '91.
"A Novel Stacked Capacitor Cell For 64Mb DRAM" by W. Wakamiye, et al., pp. 69-70, '91.

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