Method and apparatus for reducing register file access times...

Details Method and apparatus for reducing register file access times... Method and apparatus for reducing register file access times...

2005-08-23

2005-08-23

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Instruction issuing

C711S125000, C712S219000

Reexamination Certificate

active

06934830

ABSTRACT:
One embodiment of the present invention provides a system that reduces the time required to access registers from a register file within a processor. During operation, the system receives an instruction to be executed, wherein the instruction identifies at least one operand to be accessed from the register file. Next, the system looks up the operands in a register pane, wherein the register pane is smaller and faster than the register file and contains copies of a subset of registers from the register file. If the lookup is successful, the system retrieves the operands from the register pane to execute the instruction. Otherwise, if the lookup is not successful, the system retrieves the operands from the register file, and stores the operands into the register pane. This triggers the system to reissue the instruction to be executed again, so that the re-issued instruction retrieves the operands from the register pane.

REFERENCES:
patent: 5117493 (1992-05-01), Jensen
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Publication entitled “Two-Level Hierarchical Register File Organization for VLIW Processors”, by Javier Zalamea et al., IEEE, 2000, pp. 137-146.
Publication entitled “Multiple-Banked Register File Architectures”, by Jose-Lorenza Cruz et al., XP-001003052, ACM, 2000, pp. 316-325.

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