Series terminated CMOS output driver with impedance calibration

Details Series terminated CMOS output driver with impedance calibration Series terminated CMOS output driver with impedance calibration

2005-05-17

2005-05-17

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S112000, C326S030000, C326S086000, C326S087000

Reexamination Certificate

active

06894543

ABSTRACT:
A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop. A first output switch is driven by a corresponding positive control signal and connected between a supply voltage and the sources of the first and second PMOS transistors. A second output switch driven by a corresponding negative control signal and connected between a ground and the sources of the first and second PMOS transistors.

REFERENCES:
patent: 4992676 (1991-02-01), Gerosa et al.
patent: 5450019 (1995-09-01), McClure et al.
patent: 5739707 (1998-04-01), Barraclough
patent: 6133749 (2000-10-01), Hansen et al.
patent: 6201405 (2001-03-01), Hedberg
patent: 6204692 (2001-03-01), Nakagawa
patent: 6351185 (2002-02-01), Amrany et al.
patent: 0 969 633 (2000-05-01), None
patent: 0 969 633 (2002-06-01), None
patent: 6-69770 (1994-03-01), None
A copy of the European Search Report, issued Jul. 22, 2004, 3 pages.
Gabara, Thadeus J. et al., “Digitally Adjustable Resistors in CMOS for High-Performance Applications”, IEEE Journal of Solid-State Circuits, vol. 27, No. 8, Aug. 1992.

Affiliated with

Also associated with

Rating

Series terminated CMOS output driver with impedance calibration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Series terminated CMOS output driver with impedance calibration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Series terminated CMOS output driver with impedance calibration will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3460212