Self-aligned thin capacitively-coupled thyristor structure

Details Self-aligned thin capacitively-coupled thyristor structure Self-aligned thin capacitively-coupled thyristor structure

2005-06-28

2005-06-28

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Lateral structure

C257S107000

Reexamination Certificate

active

06911680

ABSTRACT:
A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor. In another implementation, the spacer is also adapted to prevent formation of salicide on the portion of the thyristor beneath the spacer, self-aligning the salicide to the junction between the second and third portions. In addition, dimensions such as width and other characteristics of the doped portions that are used to form a thyristor can be controlled without necessarily using a separate mask.

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