Power-rail ESD clamp circuit for mixed-voltage I/O buffer

Details Power-rail ESD clamp circuit for mixed-voltage I/O buffer Power-rail ESD clamp circuit for mixed-voltage I/O buffer

2005-10-11

2005-10-11

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C361S056000

Reexamination Certificate

active

06954098

ABSTRACT:
A power-rail ESD clamp circuit for mixed-voltage I/O buffer is proposed. The power-rail ESD clamp circuit comprises an ESD detection circuit and an ESD protection device. Under normal operating condition, the ESD detection circuit will not trigger the ESD protection device, and therefore the component used in the circuit will not have the gate-oxide reliability issue and also will not generate undesirable leakage current. Under ESD-zapping conditions, the ESD detection circuit will provide some trigger voltage or current to bias the ESD protection device. The ESD protection device can be triggered on quickly to discharge the ESD energy efficiently.

REFERENCES:
patent: 6147538 (2000-11-01), Andresen et al.
patent: 6633468 (2003-10-01), Duvvury et al.

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