Method for forming wirings for a semiconductor device by filling

Details Method for forming wirings for a semiconductor device by filling Method for forming wirings for a semiconductor device by filling

1987-11-27

1990-04-24

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437194, 437203, H01L 21268, H01L 21283

Patent

active

049200704

ABSTRACT:
A method for fabricating a semiconductor device with via holes, each having a width less than one micrometer and an aspect ratio more than one, assures proper filling of the via rolls with metal from a sputtered metal layer on an insulating layer having the via holes and formed on a semiconductor substrate by using a pulsed laser beam for planarization. The sputtered metal layer must be thick enough to provide the planarized metal layer with 0.5 micrometer thickness in the vicinity of the via holes for avoiding the planarized metal layer being torn around the via holes and thin enough not so as to produce caves when the sputtered metal layer is planarized by the pulsed laser beam.

REFERENCES:
patent: 4261764 (1981-04-01), Narayan
patent: 4327476 (1982-05-01), Iwai et al.
patent: 4562640 (1986-01-01), Widmann et al.
patent: 4592802 (1986-06-01), Deleonibus
patent: 4758533 (1988-07-01), Magee et al.
patent: 4800179 (1989-01-01), Mukai
Tuckerman et al., Solid State Technology, (Apr. 1986), pp. 129-134.

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