Interconnect structure with an enlarged air gaps disposed...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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Details

C257S758000, C257S760000, C438S421000, C438S422000, C438S619000, C438S637000

Reexamination Certificate

active

06940146

ABSTRACT:
An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer. The first structured dielectric layer and the second structured dielectric layer also have an opening to expose the conductive structure. When the opening is shifted to the gap region between the first conductive structure and the second conductive structure due to misalignment, the portion of the opening above the gap region stops on the anti-etch layer without opening the void.

REFERENCES:
patent: 5062508 (1991-11-01), Ackermann et al.
patent: 5814555 (1998-09-01), Bandyopadhyay et al.
patent: 6123991 (2000-09-01), Spallek et al.
patent: 6190966 (2001-02-01), Ngo et al.
patent: 6277732 (2001-08-01), Lou
patent: 6387797 (2002-05-01), Bothra et al.
patent: 6492732 (2002-12-01), Lee et al.

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