System and method for creating a limited duration clock...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

Other Related Categories

C327S198000

Type

Reexamination Certificate

Status

active

Patent number

06956414

Description

ABSTRACT:
Systems and methods for creating a limited duration clock divider reset are disclosed. Aspects of the invention may include a method for resetting a chip or a circuit. The method may include buffering a main reset input signal, inverting the main reset input signal to create an active high reset signal, resetting a counter utilizing the active high reset signal, comparing a counter output value and a counter-associated value in a comparator to obtain a comparator output value, and applying an OR logical operation to the comparator output. A limited duration clock divider reset may be generated from the output of the OR logical operation. The OR logical operation may be applied to the buffered main reset input signal. The comparator output may be inverted.

REFERENCES:
patent: 5323066 (1994-06-01), Feddeler et al.
patent: 5708381 (1998-01-01), Higashisaka
patent: 6473476 (2002-10-01), Banks
patent: 6611158 (2003-08-01), Ehmann
patent: 2004/0267848 (2004-12-01), Govindarajan
patent: 8-29496 (1996-02-01), None

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