Strapping via for interconnecting integrated circuit structures

Details Strapping via for interconnecting integrated circuit structures Strapping via for interconnecting integrated circuit structures

1995-12-05

1998-01-27

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257756, 257377, 257393, 257903, 257774, H01L 2348, H01L 2352, H01L 2940

Patent

active

057125082

ABSTRACT:
A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.

REFERENCES:
patent: 5198683 (1993-03-01), Sivan
patent: 5212399 (1993-05-01), Manning

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